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Channel Interface Processor (CIP) Installation and Configuration
Product Numbers: CX-CIP-ECA1=, CX-CIP-ECA2=, CX-CIP-ECAP1=, CX-CIP-PCA1=, CX-CIP-PCA2=, CX-CIP-ECA1, CX-CIP-ECA2, CX-CIP-ECAP1, CX-CIP-PCA1, CX-CIP-PCA2, CAB-PCA-Y=, CAB-PCA-VA=, CAB-PCA-VB=
This document contains instructions for installing (or replacing) the Channel Interface Processor (CIP) in Cisco 7000 series and Cisco 7500 series routers. For complete and detailed descriptions of CIP-related interface commands, configuration options, and requirements, refer to the Router Products Configuration Guide and Router Products Command Reference publications.
This document includes the following sections:
This section discusses the CIP and the Cisco 7000 series and Cisco 7500 series routers.
The CIP provides up to two channel-attached interfaces for Cisco 7000 series and Cisco 7500 series routers, eliminating the need for a separate front-end processor.
The CIP interfaces are combinations of a bus and tag (also called an original equipment manufacturer's interface [OEMI] and a parallel I/O interface) adapter and an Enterprise Systems Connection (ESCON) adapter.
The bus and tag adapter is called the Parallel Channel Adapter (PCA), and the ESCON adapter is called the ESCON Channel Adapter (ECA). The PCA and ECA connect directly to the CIP, and any combination of the two adapters can be used.
A mainframe channel (referred to as a channel) is an intelligent processor that manages the protocol on the communications media and controls the data transfer to and from the main central processing unit (CPU) storage. Devices called input/output processors (IOPs) communicate between the host CPU and the channel. One IOP controls multiple channels, and there is no relationship between the number of CPUs and the number of IOPs.
The channel relieves the mainframe CPU of direct communication with input/output (I/O) devices, which saves processing cycles and allows data processing and communications tasks to run concurrently. Channels use one or more channel paths as the links between mainframes and I/O devices. I/O devices are connected directly to control units, which provide the logical capabilities required to operate and control the I/O devices.
The CIP (see Figure 1) consists of a motherboard that is mounted on a metal carrier and one or two ECA and/or PCA interfaces. The ECA and PCA interfaces attach to the motherboard by means of a multipin connector located at the rear edge of the adapter.
Figure 1 : Channel Interface Processor, Horizontal Orientation
There are three CIP carrier types, which offer the following five interface adapter combinations:
The ECA has a female, duplex connector, and the PCA has a female, DB-78 connector. Figure 2 shows the ECA and PCA interface combinations.
Figure 2 : CIP Interface Adapter Combinations
Each CIP model is available in the following configurations of dynamic random-access memory (DRAM) single in-line memory modules (SIMMs):
ESCON and Bus and Tag Specifications
Table 1 lists the specifications for the ESCON and bus and tag interfaces.
Table 1 : ESCON and Bus and Tag Specifications
Following are the functions of the CIP LEDs. (See Figure 3.)
Following are the sequences for the CIP LED indicators. The enabled LED is not part of the following sequences. On cold boots, the following LED sequences apply:
The following LED sequence indicates that the CIP is waiting for commands from the RP (or RSP).
On warm boots, the LEDs flash briefly. On downloads, the following three LED sequences apply; the first indicates that the system is downloading volatile programmable logic device (VPLD) code:
The following sequence indicates that the CIP is downloading microcode:
The following sequence indicates that the CIP is starting to execute the microcode:
The ECA interface uses 62.5/125 micrometer, multimode, fiber-optic cable with male duplex connectors at each end. (See Figure 4.) ESCON cables are not available from Cisco Systems. Refer to the ESCON specifications given in Table 1 and contact your cable supplier or the vendor of your host CPU to order the correct ESCON cable.
Figure 4 : ESCON Interface Duplex Connector for the ECA
Following are descriptions and illustrations of the bus and tag cables.
Y Cable
The bus and tag cable with three 78-pin connectors (shown in Figure 5) has a DB-78 male (PCA) connector on the CIP end, a DB-78 female connector on the next-control-unit end, and a DB-78 male connector on the from-host end. The model number is CAB-PCA-Y (referred to as the Y cable) The male connector might be labeled IN and is typically black, but can also be a dark gray. The female connector might be labeled OUT and is typically light gray. The female OUT cable is nearest to the select/bypass switch, which is discussed on the following page. (The IBM part number is 89F8392; however, this is subject to change.)
Figure 5 : PCA Bus and Tag Cable, CAB-PCA-Y
Note the switch marked S (for select mode) and B (for bypass mode). The switch is located on the rear of the PCA connector. (See Figure 6.) The select/bypass switch is required to allow the cable to be separated from the PCA without "opening" the select-out loop.
Figure 6 : Select/Bypass Switch on the Rear of the PCA Connector, CAB-PCA-Y Bypass Shown
In select mode the PCA is operational, and the select-out signal is passed in a loop to all control lines on the channel. All control units have a relay that shorts the incoming select-out signal to the outgoing select-out signal when power is not applied to the control unit. When power is applied, the relay is opened, and the signal is passed to the PCA.
Without the select/bypass switch in bypass mode, the channel would need to be taken offline before servicing or replacing a CIP. If the selected address does not match, the select-out signal is passed to the next control unit. If the select-out signal gets all the way back to the channel, the control unit being addressed is not present. In bypass mode, the incoming select-out signal is shorted to the outgoing select-out signal, bypassing the downstream control unit, which is still active.
VA and VB Cables
The two bus and tag cables with connector blocks have a DB-78 (male or female) connector on the CIP end and 48-pin type-A connector blocks on the bus and tag ends. (See Figure 7.)
For the bus and tag cable that attaches between the host and the PCA, the model number is CAB-PCA-VA, and it is referred to as the VA cable. The female 78-pin connector might be labeled IN and is typically light gray. The cable labeled P2 is bus, and the cable labeled P3 is tag. Looking into the end of the female 78-pin connector (on the VA cable), with the wide part of the connector D-shell on top, the P2 (bus) cable is on the right, and the P3 (tag) cable is on the left. The plastic on the ends of the bus and tag connectors might be black or dark gray. The IBM part number is 12G8058; however, this is subject to change. The VA cable ships with a terminator; the Cisco model number CAB-PCA-VA includes this terminator. The terminator and VA cable together have the IBM part number 12G7988; however, this is subject to change.
For the bus and tag cable that attaches between the next control unit and the PCA, the model number is CAB-PCA-VB, and it is referred to as the VB cable. The male 78-pin connector might be labeled OUT and is typically black or dark gray. The cable labeled P2 is bus and the cables labeled P3 is tag. Looking into the end of the male 78-pin connector (on the VB cable), with the wide part of the connector D-shell on top, the P2 (bus) cable is on the left and the P3 (tag) cable is on the right. The plastic on the ends of the bus and tag connectors might be light gray (as opposed to the black or dark gray plastic on the VA cable). The IBM part number is 12G7933; however, this is subject to change.
Figure 7 : PCA Bus and Tag, VA and VB Cables
The Y cable always attaches to the PCA. The VA cable attaches between the male end of the Y cable and the host. The VB cable attaches between the female end of the Y cable and the next (or new) control unit. Do not connect VB cable directly to the PCA. If the PCA is the last control unit, channel termination is required at the end of the Y cable that points away from the host. (See Figure 5.) For attachment instructions refer to the section "Attaching the CIP to the Channel" on page 24.
What Are the Cisco 7000 and Cisco 7500 Series?
For the Cisco 7000 and Cisco 7500 series routers, network interfaces reside on modular interface processors, which provide a direct connection between external networks and the high-speed CxBus in the Cisco 7000 series and the high-speed CyBus in the Cisco 75oo series.
In all systems, the remaining slots support any combination of network interface types: Ethernet, Fast Ethernet, Asynchronous Transfer Mode (ATM), Token Ring, multichannel applications, Fiber Distributed Data Interface (FDDI), channel attachment, serial, or High-Speed Serial Interface (HSSI).
Figure 8 and Figure 9 show the rear of the Cisco 7000 series routers: the seven-slot Cisco 7000 and the five-slot Cisco 7010, respectively. In the Cisco 7000 series, two slots are reserved for the Route Processor (RP), which contains the system processor, and the Switch Processor (SP) (or Silicon Switch Processor [SSP]), which performs packet switching functions. The remaining slots are for interface processors: slots 0 through 4 in the Cisco 7000 and slots 0 through 2 in the Cisco 7010.
Figure 8 : Cisco 7000, Interface Processor End
Figure 9 : Cisco 7010, Interface Processor End
Figure 10, Figure 11, and Figure 12 show the Cisco 7500 series routers: the Cisco 7505, the Cisco 7507, and the Cisco 7513, respectively. In the Cisco 7505, one slot (4) is reserved for the Route Switch Processor (RSP1), which contains the system processor and performs packet switching functions. Slots 0 through 3 are for interface processors.
Figure 10 : Cisco 7505, Interface Processor End
Figure 11 shows the rear of the seven-slot Cisco 7507 router. In the Cisco 7507, up to two slots (2 and 3) are reserved for the Route Switch Processor (RSP2), which contains the system processor and performs packet switching functions. Slots 0 and 1, and 4 through 6 are for interface processors.
Figure 11 : Cisco 7507, Interface Processor End
Figure 12 shows the rear of the Cisco 7513, with two AC-input power supplies installed. Two slots (6 and 7) are reserved for the second generation Route Switch Processor (RSP2), which contains the system processor and performs packet-switching functions. Slots 0 through 5, and 8 through 12 are for interface processors.
Figure 12 : Cisco 7513, Interface Processor End
The CIP supports online insertion and removal (OIR), which allows you to install or remove a CIP while the system is operating, without shutting down system power.
Before you install the CIP, review the safety and electrostatic discharge (ESD)-prevention guidelines in this section to avoid injuring yourself or damaging the equipment. This section also provides a list of parts and tools you will need to perform the installation, and lists the software and microcode requirements.
This section lists safety guidelines you should follow when working with any equipment that connects to electrical power or telephone wiring.
Follow these basic guidelines when working with any electrical equipment:
Use the following guidelines when working with any equipment that is connected to telephone wiring or to other network cabling:
Preventing Electrostatic Discharge Damage
ESD damage, which can occur when electronic cards or components are improperly handled, results in complete or intermittent failures. Each processor module contains a printed circuit card that is fixed in a metal carrier. Electromagnetic interference (EMI) shielding, connectors, and a handle are integral components of the carrier. Although the metal carrier helps to protect the board from ESD, use an ESD-preventive wrist or ankle strap whenever you handle any electronic system component.
Following are guidelines for preventing ESD damage:
Online Insertion and Removal---An Overview
The OIR feature allows you to remove and replace interface processors while the system is operating; you do not need to notify the software or shut down the system power.
Each interface processor contains a male connector with which it connects to the system backplane. Each card (male) connector comprises a set of tiered pins, in three lengths. The pins send specific signals to the system as they make contact with the backplane. The system assesses the signals it receives and the order in which it receives them to determine what event is occurring and what task it needs to perform, such as reinitializing new interfaces or shutting down removed ones.
For example, when inserting an interface processor, the longest pins make contact with the backplane first, and the shortest pins make contact last. The system recognizes the signals and the sequence in which it receives them. The system expects to receive signals from the individual pins in this logical sequence, and the ejector levers help to ensure that the pins mate in this sequence.
When you remove or insert an interface processor, the backplane pins send signals to notify the system, which then performs as follows:
The system brings on line only interfaces that match the current configuration and were previously configured as up; all others require that you configure them with the configure command.
OIR functionality enables you to add, remove, or replace interface processors with the system online, which provides a method that is seamless to end users on the network, maintains all routing information, and ensures session preservation.
You need the following tools and parts to install or replace a CIP. If you need additional equipment, contact a customer service representative for ordering information.
The CIP is compatible in the Cisco 7000 series routers with Cisco Internetworking Operating System (Cisco IOS) Release 10.2(6) or later.
The CIP is compatible in the Cisco 7500 series routers with Cisco IOS Release 10.3(7), or later, and Cisco IOS Release 11.0(3) or later.
The show version and show hardware commands display the current hardware configuration of the router, including the system software version that is currently loaded and running. The show microcode command lists the bundled microcode (target hardware) version for each processor type. The show controller cxbus or show controller cbus commands show the microcode version you are running. (For complete descriptions of show commands, refer to the Router Products Configuration Guide and Router Products Command Reference publications.)
You can determine the current version of software or microcode stored in read-only memory (ROM) either by removing the processor module and checking the ROM labels or by configuring the system to boot the system software or microcode from ROM, reloading the system, and using show commands to check the version that is loaded and running. Refer to the section "Configuring Microcode" on page 30 for basic configuration information, and to the appropriate software documentation for complete configuration instructions and examples.
If the displays indicate that the required system software and microcode is not available in your system, contact a customer service representative for upgrade information. (Refer to the section "Cisco Information Online" on page 35.)
In the Cisco 7000 series, the CIP is compatible with SP Microcode Version 10.4 or later and SSP Microcode Version 10.4 or later. In the Cisco 7500 series, the SP and SSP are not used so there is no similar requirement.
Microcode, also known as firmware, is a set of processor-specific software instructions that enables and manages the features and functions of a specific processor type. At system startup or reload, the system loads the microcode for each processor type present in the system. The latest available microcode image for each processor type is bundled and distributed with the system software image. The CIP microcode boot image resides in ROM socket U37. (See Figure 1 on page 3.) The entire CIP microcode image is located in the software/microcode bundle.
New microcode is released to enable new features, improve performance, or fix bugs in earlier versions. The Cisco 7000 series and Cisco 7500 series routers feature downloadable software and microcode for most upgrades. These features enable you to download new (upgraded) images remotely, store the images in router memory, and load the new images at system startup without having to physically access the router. You can store multiple versions for a specific processor type in Flash memory, and use configuration commands to specify which version the system should load at startup. All interfaces of the same type (for example, all CIPs) use the same microcode image. Although most upgrades can be downloaded, some exceptions require ROM replacement to ensure proper startup and operation.
Microcode images that are bundled with the system image load automatically along with the new software image. Refer to the section "Configuring Microcode" on page 30 for instructions.
The following sections provide a functional overview of online insertion and removal (OIR), and describe the procedures for installing or replacing CxBus interface processors in Cisco 7000 series routers. Before installing any new interfaces, ensure that your system meets the minimum software and microcode requirements described in the sections "Software Prerequisites" and "Microcode Prerequisites" on page 18.
The OIR feature allows you to remove and install a CIP without turning off system power. However, you must follow the insertion instructions carefully; for example, failure to use the ejector levers or insert the CIP properly can cause system error messages indicating a card failure.
Each unused interface processor slot contains an interface processor filler (which is an interface processor carrier without an interface card) to keep dust out of the chassis and to maintain proper airflow through the interface processor compartment. If you install a new CIP, select an empty interface processor slot and remove the interface processor filler. If you replace a CIP, you can retain the existing interface configuration by removing the existing interface processor and installing the new one in the same slot; however, the new CIP must be the same hardware type as the CIP you replaced.
Following the OIR overview, proceed to the section "Removing a CIP or an Interface Processor Filler" on page 20 for instructions on making an interface processor slot available for the new CIP, then to the section "Installing a CIP" on page 23 for the installation instructions. After the new CIP is secure, follow the procedures in the section "Checking the Installation" on page 28 to verify that it is installed and functioning properly.
Removing a CIP or an Interface Processor Filler
The CIP supports OIR, so you do not need to shut down the interface or the system power when you remove a CIP; however, to prevent a possible interface control check on the mainframe, consult with your system administrator to take appropriate precautions. If you are installing a new CIP, select an available slot and remove the interface processor filler. If you are replacing a CIP, first remove the existing CIP and immediately place it component side up on an antistatic surface, then insert the new CIP in the same slot to retain the previous configuration for the new channel interface.
Figure 13 shows proper handling of an interface processor for installation in the Cisco 7010 or Cisco 7505 models. The processor slots are oriented horizontally in the Cisco 7010 and Cisco 7505, and vertically in the Cisco 7000, Cisco 7507, and Cisco 7513. When installing interface processors in these latter chassis, handle the interface processor in the same manner, but rotated 90 degrees clockwise.
Figure 13 : Handling Interface Processors during Installation
Figure 14 shows the functions of the ejector levers in the correct orientation for the horizontal processor slots in a Cisco 7010 and Cisco 7505 chassis. In a Cisco 7000, Cisco 7507, and Cisco 7513 chassis, the function of the ejector levers is the same, but the orientation is rotated 90 degrees clockwise for the vertical processor slots.
Figure 14 : Function of the Ejector Levers
The function of the ejector levers (see Figure 14) is to align and seat the card connectors in the backplane. Failure to use the ejector levers and insert the interface processor properly can disrupt the order in which the pins make contact with the backplane.
Following are examples of incorrect insertion practices and their results:
Using the ejector levers and making sure that they are pushed fully into position ensures that all three layers of pins are mated with (or free from) the backplane.
It is also important to use the ejector levers when you remove an interface processor to ensure that the card connector pins disconnect from the backplane in the logical sequence expected by the system. Any processor module that is only partially connected to the backplane can halt the bus. Detailed steps for correctly performing OIR are included with the following removal and installation procedures.
Refer to Figure 14 while performing the following steps to remove a CIP or interface processor filler. If you are removing an interface processor filler, proceed to step 5. If you are replacing an existing CIP, begin at step 1. In the following procedures, two channel-related terms are used: vary offline refers to disabling an interface; vary online refers to enabling an interface. For instructions on how to vary the host channel or addresses online or offline, refer to the documentation for your operating system.
This completes the removal procedure. Proceed to the next section to install a new CIP.
The CIP slides into any available interface processor slot and connects directly to the backplane of the Cisco 7000 series or Cisco 7500 series router. The backplane slots are keyed so that the CIP can be installed only in an interface processor slot. (Refer to Figure 8, Figure 9, Figure 10, Figure 11, or Figure 12, depending on your chassis type.) Figure 14 shows the functional details of inserting an interface processor and using the ejector levers. Figure 13 shows proper handling of an interface processor during installation.
Follow these steps to install a CIP:
Proceed to the next section to attach the bus and tag and/or ESCON cables between the CIP interface ports and your channel.
Attaching the CIP to the Channel
The CIP can be connected to the channel using the bus and tag cables (for the PCA) and/or using a fiber-optic ESCON cable with duplex connectors (for the ECA). Bus and tag and ESCON connections each have their own special requirements. The following sections discuss bus and tag and ESCON connections.
Attaching the Bus and Tag Cables
The PCA is connected using the bus and tag cable with 78-pin connectors (the Y cable) and the bus and tag cables with 48-pin, type A connector blocks (the VA and VB cables). In general, a Y cable attaches to the PCA on the CIP and the VA and VB cables attach to the remaining ends of the Y cable.
Attaching the PCA to the Host Channel
Attach the PCA to the host as follows.
Figure 15 : Connecting or Removing the Y Cable
Figure 16 : Connecting the VB Cable Between the Y Cable and the Next Control Unit
Figure 17 : Straight-Through Cable
Figure 18 : Connecting the VA Cable Between the Y Cable and the Host
Detaching the Y Cable from the PCA
To properly detach a Y cable from the PCA, use the following procedure.
Following is the procedure for attaching the ESCON cable between the ECA and the host channel.
Figure 19 : Connecting an ESCON Cable to the ECA
After you install the CIP and cables, verify the installation by observing the LED states and the console display. When the system has reinitialized all interfaces, the enabled LED on the CIP (and on all interface processors) should go on. The console screen will also display a message as the system discovers each interface during its reinitialization.
If you need to verify the operation of the interfaces, refer to the section "Diagnostic Tests" on page 33.
When you remove and replace interface processors, the system provides status messages on the console screen. These messages are for information only. The following sample display shows the events logged by the system as a CIP was removed from slot 1; the system then reinitialized the remaining interface processors and marked as down the CIP that was removed from slot 1. When the CIP was reinserted, the system marked the interface as up again because the interface was not shut down before the CIP was removed.
The sample display follows:
When a new CIP is inserted or when a CIP is moved to a new slot, the system recognizes the new interface, but leaves it in a down state until you configure it and change the state to up with the no shutdown command.
The following sample display shows the events logged by the system as a new single-PCA CIP is inserted in slot 3:
Verify that the CIP is installed correctly, as follows:
Figure 20 : CIP LED Indicators
If an error message is displayed on the console terminal, refer to the System Error Messages publication for error message definitions. If you experience other problems that you are unable to solve, contact a service representative for assistance.
This completes the CIP hardware installation.
At system startup or reload, the system loads a microcode image for each processor type. The default is to bypass the ROM microcode and load the microcode images bundled with the system software.
All processors of the same type use the same microcode image; only one image for each type can load at startup. This section describes how to modify the startup configuration to load different microcode images at startup, or to change existing configuration instructions and reenable the system default.
The CIP ROM provides a CIP microcode boot image. The entire CIP microcode image is located in the bundle.
Whenever you upgrade software or microcode by downloading new images into Flash memory, you must configure the system to load the new image at startup. Otherwise, the system will continue to load the default image from the system, or attempt to load the previous image (if any) if it is still specified in the configuration file.
Also, if you are upgrading to a release that uses bundled images, you must also remove any previous instructions from the configuration file that would prevent any new images from loading. For example, if the configuration file contains instructions to load the CIP microcode from a file named cip1-1 in Flash memory, the system will continue to follow those instructions at startup and prevent the newer CIP microcode image, which is bundled with the system image, from loading.
To instruct the system to boot a CIP microcode image other than the default at startup, use the microcode interface-type [system | flash] filename configuration command to add the instructions to the configuration file. The system option tells the system to load from the system bundle. All processors of the same type (for example, all CIPs) will load the same microcode image, either from the default source or from the source you specify.
Follow these steps to configure the microcode for a specific processor:
This completes the procedure for configuring microcode. For complete descriptions of the show commands, refer to the Router Products Configuration Guide and Router Products Command Reference publications.
The microcode boot image ROM device on the CIP is located at socket location U37. (See Figure 21.) Typically, it is not necessary to replace this ROM; however, should it become necessary, instructions are located in the publication Upgrading System Software and Microcode in Cisco 7000 Series Routers (Document Number 78-1144-xx), which is shipped with each new microcode (and software) bundle.
Figure 21 : CIP Microcode ROM Location, Vertical Orientation
This reference section provides a summary of the diagnostic test routines that you can use to verify the current system status, a list of related documentation, and includes phone numbers for obtaining technical assistance.
There are six PCA and ECA diagnostic test routines.
The six diagnostic tests are as follows:
The interface has to pass the first five tests. The sixth test (which is the same as the fifth, but with a different mode for the optical wrap plug for the ECA, instead of electrically wrapping the interface) will fail if no wrap plug is installed or if the interface is connected to the channel. This type of failure will not affect the channel.
If a wrap plug is inserted, following is how the wrap diagnostics will be repeated:
If you suspect that an adapter might be the cause of a problem you are seeing, you can run a single pass of the diagnostic tests on an installed PCA or ECA interface by entering configuration mode and specifying that the console terminal will be the source of the configuration subcommands, as follows:
Next, specify the slot/port number (interface processor slot number/port number) of the interface for which you want the diagnostic tests to run, by entering the interface channel command, followed by the slot/port of the interface.
The example that follows is for a CIP interface in interface processor slot 1:
The no shutdown command causes the diagnostic tests to run on the PCA or ECA interface you selected. If no failures occur, you can rule out that adapter as the source of your problem.
Following are the related (and orderable) publications referenced in this document:
All documents listed above are available on UniverCD or in print.
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Characteristic
ESCON
Bus and Tag
Supported processor I/O architectures
ESA/390
System/370
370/Xa
ESA/390
Bit transmission
Serial
Parallel
Maximum distance (for LED with ESCON)
1.9 miles (3.1 km) point-to-point
5.7 miles (9.2 km) with two ESCON Directors
400 ft (122 m)1
Channel data rate
Up to 17 MBps2
Up to 4.5 MBps
Signaling rate3
200 Mbps4
4.5 MBps
Cable types
Fiber-optic (62.5/125 micron multimode)
Copper bus and tag
Connection types
Dynamic5
Static
Number of addressable devices per channel
256 x 16 x 16 x 2536
256
Connectable control units per channel
Up to 59 (through a 9032 ESCON Director)
Up to 8
Connectable channels per adapter
Up to 59 (through a 9032 ESCON Director)
Varies by control unit
1
1 The IBM 3044 C/D (host side/remote side) copper-to-fiber repeater can be used to extend this distance up to 1.2 miles (2 km).
2 MBps = megabytes per second.
3 For bus and tag, the signaling rate matches the channel data rate. For example, if you use a 3.0 MBps channel, the signaling rate is 3.0MBps. The ESCON interface signals at a constant rate; the bus and tag interface signals at the data rate.
4 Mbps = megabits per second.
5 The CIP ESCON requires dynamic = NO with HCD.
6 Where 256 represents available unit addresses, 16 represents the number of partitions (LPARs), 16 represents the number of control unit images, and 253 represents the number of ESCON director paths. It is unlikely a system would have the resources to support the total number of available addresses.
Present
Loaded
Signal
Online
Port 1
On
On
Off
Off
Port 0
Off
Off
Off
Off
Present
Loaded
Signal
Online
Port 1
On
On
On
On
Port 0
On
On
Off
Off
Present
Loaded
Signal
Online
Port 1
On
On
On
On
Port 0
On
On
On
On
Present
Loaded
Signal
Online
Port 1
Off
Off
Off
Off
Port 0
Off
Off
Off
Off
Present
Loaded
Signal
Online
Port 1
On
On
On
On
Port 0
On
On
On
Off
Present
Loaded
Signal
Online
Port 1
Off
Off
Off
Off
Port 0
On
On
On
On
Present
Loaded
Signal
Online
Port 1
Off
Off
Off
Off
Port 0
Off
Off
Off
Off
Router#
%OIR-6-REMCARD: Card removed from slot 1, interfaces disabled
%LINK-5-CHANGED: Interface CIP1/0, changed state to administratively down
Router#
%OIR-6-INSCARD: Card inserted in slot 1, interfaces administratively shut down
%LINK-5-CHANGED: Interface CIP1/0, changed state to up
Router#
%OIR-6-INSCARD: Card inserted in slot 3, interfaces administratively shut down
Route>
show flash
4096K bytes of flash memory on embedded flash (in RP1).
file offset length name
0 0x40 462500 cip1-1
[3678246/3787214 bytes free]
Router>
enable
Password:
Router#
Router#
configure terminal
microcode cip flash cip1-1
no microcode cip flash cip1-1
Router#
copy running-config startup-config
Router# configure terminal
interface channel 1/0
shutdown
no shutdown
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Footnotes
